A Signal processing technique known as correlated double sampling is commonly used to eliminate noise in a signal which needs to be correlated. An example of such a signal is the image signal from a solid state imaging device (such as a charge-coupled device (CCD) image sensor) in order to obtain low noise performance. Correlated double sampling is equivalent to subtracting a reset reference level (V.sub.reset) from an image level (V.sub.image) for each output pixel from the CCD image sensor.
A CCD output circuit, shown in FIG. 1, converts the photoelectrically generated signal charge to a voltage signal. Charge packets from the CCD imager photosites (not shown) are transferred into a horizontal shift register 10. The charge packets are shifted horizontally via horizontal clocks H1 and H2 and onto a floating diffusion node 12 via output gate 13. The potential of the floating diffusion node 12 changes linearly in proportion to the number of electrons in the charge packet. The potential of the floating diffusion node 12 is applied to the input gate of a two stage source follower circuit 14, producing a signal at V.sub.out. A reset transistor 16 driven by the reset clock RESET recharges the floating diffusion node 12 to the positive potential V.sub.rd before the arrival of each new charge packet from the horizontal shift register 10.
FIG. 2(A) shows the signal waveform V.sub.out at the output of the source follower 14 of FIG. 1. The waveform contains three components: the reset clock feedthrough (V.sub.ft), the reset reference level (V.sub.reset), and the image level (V.sub.image). The feed through V.sub.ft occurs as a result of capacitive coupling between the RESET gate 16 and the floating diffusion node 12. When the floating diffusion 12 is reset, the exact reset voltage is affected by "thermal" noise, whose level depends on the capacitance of the floating diffusion node 12 and the temperature. The same random reset noise voltage affects the level of both the reference level V.sub.reset and the image level V.sub.image. By taking the difference between samples of V.sub.reset and V.sub.image for each pixel, this "thermal" noise can be eliminated. This also reduces low frequency noise from the two stage source follower output amplifier 14.
A commonly known circuit for performing correlated double sampling is shown in FIG. 3 (see, for example, the circuits disclosed in U.S. Pat. Nos. 4,283,742 and 4,845,382). The signal V.sub.out from the circuit of FIG. 1 forms the input signal V.sub.in to sample/hold circuits 20 and 22, and the output of the sample/hold circuit 20 is further sampled by a sample/hold circuit 24. The aforementioned difference signal V.sub.D is taken between the outputs of the sample/hold circuits 22 and 24 by a subtracting circuit 26. FIGS. 2(B) and 2(C) show the sampling waveforms S/H(1) and S/H(2) that respectively drive the sample/hold circuit 20, and the sample/hold circuits 22 and 24. Sampling pulses from the waveform S/H(1) cause the sample/hold circuit 20 to sample the resent reference level (V.sub.reset). Sampling pulses from the waveform S/H(2) cause the sample/hold circuit 22 to sample the image level (V.sub.image), while simultaneously causing the sample/hold 24 to sample the output of the sample/hold circuit 20, thus effecting a delay in the reset reference level (V.sub.reset). A noise-free image signal V.sub.D (shown in FIG. 2(D)) is then obtained from the differencing circuit 26 by taking the difference between the outputs of the sample/hold circuits 22 and 24.
Another correlating circuit shown in FIG. 4 utilizes a delay line and sample-and-hold circuits U.S. Pat. No. 4,287,441, issued Sep. 1, 1981, inventor Smith. As shown in FIG. 4, a low gain high current buffer/driver 81 is capacitively coupled to the output of the CCD. The output of this amplifier is fed to two nearly identical channels. The input of one channel has a delay line 82, while the input of the second channel has only an attenuator 83. Each channel has a sample-and-hold circuit 84 and 85, operating from the same source of clock pulses 86. The output of each channel is fed to one input of a differential amplifier 87. In some cases a midstage sample-and-hold 88 may be included at the output of the differential amplifier. Sample and hold circuit 88 is operated in synchronism with circuits 84 and 85. A high gain amplifier 89 can also be coupled to the output of the midstage S&H. The total circuit gain G is divided between these two amplifier elements.
The input S/H 84 with delay 82 is strobed to acquire the reference level signal; the input S/H 85 without delay, simultaneously strobed, acquires the video level signal within the same basic period.
U.S. Pat. No. 5,086,344, issued Feb. 4, 1992, inventors D'Luna et al., discloses a digital correlated double sampling circuit for sampling the output of an image sensor. The digital correlated double sampling circuit employs three resisters and a single clock signal to sample the output of a charge transfer device. The first register samples the reset reference value on the falling edge of the master clock cycle while the remaining two registers sample on the rising edge. The second register samples the image level and the third register samples the output of the first register, thus effecting a delay of the reset reference level. The outputs of the second and third registers, that is, the image level and the reset reference level, are differenced to provide a noise-free image signal.
A problem exists in the correlator signal processing circuits disclosed in these patents. Since these circuits use active circuit elements (e.g., sample and hold circuits) which rely on additional timing and control circuitry for operation, the prior art correlator circuits are complex and expensive.